Vers les sources optiques compatibles CMOS : corrélation entre élaboration et propriétés des nanocristaux de Si par LPCVD

Les systèmes sur puce comportant des fonctions optiques ont un vif intérêt pour les futures générations de systèmes embarqués, les telecommunications, l'instrumentation. La faisabilité d'une source silicium compatible avec la technologie CMOS reste à ce jour un verrou majeur pour ouvrir la voie à des systèmes optoélectroniques intégrés. L'utilisation des nanocristaux de silicium dans une matrice de SiO2 est actuellement une voie prometteuse visant à lever ce verrou. L'objectif de cette thèse est d'étudier la faisabilité de sources émettant dans le visible/proche infrarouge à base de nanocristaux de silicium, en explorant les potentialités de dépôts LPCVD (Low Pressure Chemical Vapor Deposition). En partant de l'étude des propriétés des nanocristaux, une approche bottom-up a été choisie pour la réalisation des composants de test. Un procédé d'élaboration du matériau actif, compatible avec la technologie CMOS, a été mis au point et nous a permis d'obtenir de façon reproductible des nanocristaux avec les propriétés souhaitées. Les mécanismes d'émission lumineuse ont été étudiés et corrélés avec les propriétés structurales et électriques. Une émission lumineuse intense a été obtenue sous excitation optique. L'obtention d'électroluminescence nécessite quant à elle une optimisation spécifique tant au niveau matériau qu'au niveau procédé technologique. A cette fin, plusieurs voies ont été explorées nous conduisant à établir le compromis entre propriétés optiques et électriques. Au terme de cette étude, nous avons évalué les avantages et inconvénients de cette technique d'élaboration et proposons des solutions pour parvenir à fabriquer un dispositif électroluminescent fonctionnel.Integrated systems comprising on-chip optical functions are of great interest for future generations of embedded, telecommunications sensing and instrumentation applications. The feasibility of a Silicon light source, compatible with CMOS technology remains a major hurdle in the development of systems combining optical and electronic functions on the same chip. The use of silicon nanocrystals embedded in a SiO2 matrix seems to be a promising solution. The objective of this work is to study the feasibility of visible/near infrared light sources using silicon nanocrystals obtained by LPCVD (Low Pressure Chemical Vapor Deposition). Starting with a study of the material properties, we chose a bottom-up approach to fabricate several test devices. A reproducible, CMOS compatible technological process has been established to obtain the active material with the desired properties. The mechanisms of light emission have been studied by different characterization techniques and correlated with the structural and electrical properties. We have obtained intense emission under optical excitation in the visible/near infrared domain. Electroluminescence, however, requires a specific optimization of the active layer. We have explored several different implementations and have identified the tradeoffs between optical and electrical properties. At the end of this study, we have evaluated the advantages and disadvantages of LPCVD as a fabrication method for Si nanocrystals and propose solutions for the implementation of a functional electroluminescent device

Generalized empirical Bayesian methods for discovery of differential data in high-throughput biology

Motivation: High-throughput data are now commonplace in biological research. Rapidly changing technologies and application mean that novel methods for detecting differential behaviour that account for a ‘large P, small n’ setting are required at an increasing rate. The development of such methods is, in general, being done on an ad hoc basis, requiring further development cycles and a lack of standardization between analyses. Results: We present here a generalized method for identifying differential behaviour within high-throughput biological data through empirical Bayesian methods. This approach is based on our baySeq algorithm for identification of differential expression in RNA-seq data based on a negative binomial distribution, and in paired data based on a beta-binomial distribution. Here we show how the same empirical Bayesian approach can be applied to any parametric distribution, removing the need for lengthy development of novel methods for differently distributed data. Comparisons with existing methods developed to address specific problems in high-throughput biological data show that these generic methods can achieve equivalent or better performance. A number of enhancements to the basic algorithm are also presented to increase flexibility and reduce computational costs. Availability and implementation: The methods are implemented in the R baySeq (v2) package, available on Bioconductor http://www.bioconductor.org/packages/release/bioc/html/baySeq.html. Contact: [email protected] Supplementary information: Supplementary data are available at Bioinformatics online.This work was supported by European Research Council Advanced Investigator Grant ERC-2013-AdG 340642 – TRIBE.This is the author accepted manuscript. The final version is available from Oxford University Press via http://dx.doi.org/10.1093/bioinformatics/btv56

Efficient Execution Paradigms for Parallel Heterogeneous Architectures

This thesis proposes novel, efficient execution-paradigms for parallel heterogeneous architectures. The end of Dennard scaling is threatening the effectiveness of DVFS in future nodes; therefore, new execution paradigms are required to exploit the non-linear relationship between performance and energy efficiency of memory-bound application-regions. To attack this problem, we propose the decoupled access-execute (DAE) paradigm. DAE transforms regions of interest (at program-level) in two coarse-grain phases: the access-phase and the execute-phase, which we can independently DVFS. The access-phase is intended to prefetch the data in the cache, and is therefore expected to be predominantly memory-bound, while the execute-phase runs immediately after the access-phase (that has warmed-up the cache) and is therefore expected to be compute-bound. DAE, achieves good energy savings (on average 25% lower EDP) without performance degradation, as opposed to other DVFS techniques. Furthermore, DAE increases the memory level parallelism (MLP) of memory-bound regions, which results in performance improvements of memory-bound applications. To automatically transform application-regions to DAE, we propose compiler techniques to automatically generate and incorporate the access-phase(s) in the application. Our work targets affine, non-affine, and even complex, general-purpose codes. Furthermore, we explore the benefits of software multi-versioning to optimize DAE in dynamic environments, and handle codes with statically unknown access-phase overheads. In general, applications automatically-transformed to DAE by our compiler, maintain (or even exceed in some cases) the good performance and energy efficiency of manually-optimized DAE codes. Finally, to ease the programming environment of heterogeneous systems (with integrated GPUs), we propose a novel system-architecture that provides unified virtual memory with low overhead. The underlying insight behind our work is that existing data-parallel programming models are a good fit for relaxed memory consistency models (e.g., the heterogeneous race-free model). This allows us to simplify the coherency protocol between the CPU – GPU, as well as the GPU memory management unit. On average, we achieve 45% speedup and 45% lower EDP over the corresponding SC implementation.UPMAR

Vers les sources optiques compatibles CMOS (corrélation entre élaboration et propriétés des nanocristaux de Si par LPCVD)

TOULOUSE3-BU Sciences (315552104) / SudocSudocFranceF

Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead

This work proposes a novel scheme to facilitate heterogeneous systems with unified virtual memory. Research proposals implement coherence protocols for sequential consistency (SC) between central processing unit (CPU) cores and between devices. Such mechanisms introduce severe bottlenecks in the system; therefore, we adopt the heterogeneous-race-free (HRF) memory model. The use of HRF simplifies the coherency protocol and the graphics processing unit (GPU) memory management unit (MMU). Our protocol optimizes CPU and GPU demands separately, with the GPU part being simpler while the CPU is more elaborate and latency aware. We achieve an average 45% speedup and 45% energy-delay product reduction (20% energy) over the corresponding SC implementation.UPMAR

Towards Power Efficiency on Task-Based, Decoupled Access-Execute Models

This work demonstrates the potential of hardware and software optimization to improve theeffectiveness of dynamic voltage and frequency scaling (DVFS). For software, we decouple data prefetch (access) and computation (execute) to enable optimal DVFS selectionfor each phase. For hardware, we use measurements from state-of-the-art multicore processors to accurately model the potential of per-core, zero-latency DVFS. We demonstrate that the combinationof decoupled access-execute and precise DVFS has the potential to decrease EDP by 25-30% without reducing performance. The underlying insight in this work is that by decoupling access and execute we can take advantageof the memory-bound nature of the access phase and the compute-bound nature of the execute phase to optimize power efficiency. For the memory-bound access phase, where we prefetch data into the cachefrom main memory, we can run at a reduced frequency and voltage without hurting performance. Thereafter, the execute phase can run much faster, thanks to the prefetching of the access phase, and achieve higher performance. This decoupled program behavior allows us to achieve more effective use of DVFS than standard coupled executions which mix data access and compute. To understand the potential of this approach, we measure application performance and power consumption on a modern multicore system across a range of frequencies and voltages. From this data we build a model that allows us to analyze the effects of per-core, zero-latency DVFS. The results of this work demonstrate the significant potential for finer-grain DVFS in combination with DVFS-optimized software